This invention relates in general to techniques for driving liquid crystal displays and in particular, to a technique, circuit, and bus structure for driving a row of pixels in an active matrix liquid crystal display.
U.S. Pat. No. 3,862,360 issued to Dill et. al., describes one construction of an active matrix liquid crystal display ("AMLCD"). The AMLCD is formed by confining a thin layer of liquid crystal material between two plates. One plate is typically a glass plate (also referred to herein as "front plate"), which has one large transparent electrode formed on a surface adjacent to the confined liquid crystal material. The other plate, is a processed silicon substrate (also referred to herein as "back plate"), which has a plurality of reflective electrodes formed on a surface adjacent to the confined liquid crystal material.
When an electric potential is applied across one of the back plate reflective electrodes and the front plate electrode (i.e., activating a "pixel"), the molecular alignment of the liquid crystal material between the two electrodes is altered. Depending upon the type of liquid crystal material being used, the liquid crystal material then acts as either a light valve or a light scattering medium to incident light entering through the front plate, passing through the liquid crystal material, and then being reflected back through the liquid crystal material and the front plate by the reflective electrode. For a general discussion on the structure and operation of such active matrix liquid crystal displays, see, e.g., Kaneko, E., LIQUID CRYSTAL TV DISPLAYS, KTK Scientific Publishers, Tokyo, 1987.
FIG. 1 illustrates an example of a portion of a conventional circuit used for activating selected pixels in a matrix array of pixels. Each pixel (e.g., 14) has a field effect transistor ("FET") and a storage capacitor associated with it which act together as an elemental sample and hold circuit for the pixel. For example, when a gate signal 5 is applied to a gate 16 of a FET 10, a display signal 3 being applied to a drain 18 of the FET 10 is "sampled" and charges a storage capacitor 12 which is connected to a source 15 of the FET 10. The storage capacitor 12 then "holds" the voltage provided by the display signal 3 for a pixel 14.
To drive a row of pixels in a matrix of pixels organized in rows and columns, a conventional technique is to provide pixel display signals along spaced apart, parallel column buses (e.g., 200, 210 and 220) which are properly timed with row scanning signals being sequentially provided to spaced apart, parallel row buses (e.g., 100 and 110). The storage capacitors associated with each row of pixels are then "refreshed" with the desired line image each time a row scanning signal is applied to the gates of the FETs associated with that row of pixels, and "hold" that line image for the row of pixels while other rows are being refreshed.
For example, when a row scanning signal 5 is provided to a row bus 100, each of the FETs (e.g., 10, 20 and 30) whose gate electrodes (16, 26 and 36, respectively) are connected to the row bus 100 pass display signals being provided to their drains (18, 28 and 38, respectively) along column buses (200, 210 and 220, respectively) to storage capacitors (12, 22 and 32, respectively) connected to the sources (15, 25 and 35, respectively) of the FETs (e.g., 10, 20 and 30). The storage capacitors (12, 22 and 32) then hold those voltages provided by the display signals while the next row of storage capacitors (e.g., 42, 52 and 62) is being charged by new display signals being provided over column buses (200, 210 and 220, respectively) while a row scanning signal is being applied to the next row bus 110.
FIG. 2A illustrates an example of a top plan view of part of a back plate for a conventional active matrix liquid crystal display of the type previously described, and FIGS. 2B and 2C illustrate cross-sectional cut-out views of that part of the back plate through lines 2B and 2C, respectively, of FIG. 2A. In particular, the figures illustrate a top plan view and cross-sectional views of two reflective electrodes, 240' and 340' along with certain circuit elements for driving the two electrodes. The figures are provided for illustrational purposes only, and are not intended to be drawn to scale nor laid out in any particular manner. Common reference numbers in the figures refer to the same elements being depicted.
Referring to FIGS. 2A-2C, the reflective electrodes, 240' and 340', and their respective drive circuitry are formed on the back plate of one type of active matrix liquid crystal display by first forming the drain (e.g., 21') and source (e.g., 23') regions of FETs in a top surface of a silicon substrate 70, and then forming a field oxide layer 71 over the top surface of the silicon substrate 70. Using conventional techniques, the field oxide layer 71 is then selectively etched away over channel areas (e.g., 24') of the FETs, and a thin oxide layer 72 is then formed over these channel areas (e.g., 24').
A polysilicon gate bus 100' (also referred to herein as a "row bus" or a "scanning electrode bus") is then formed along with polysilicon gate electrodes (e.g., 105') and polysilicon storage capacitor electrodes (e.g., 22') for each of the FETs. This is generally done by a conventional technique of depositing a layer of polysilicon material (also referred to as "polycrystalline silicon" material) over the field oxide layer 71 and the thin oxide layer 72, and then selectively removing portions of that layer so as to leave behind the polysilicon gate bus 100', gate electrodes (e.g., 105'), and storage capacitor electrodes (e.g., 22').
Another oxide layer 73 is then formed over the field oxide layer 71, polysilicon gate bus 100' gate electrodes (e.g., 105'), and storage capacitor electrodes (e.g., 22'). Using conventional techniques, holes (e.g., 25") are then formed in the oxide layers 71 and 73 which extend from the top of the oxide layer 73 down to the drain regions (e.g., 21').
column buses (e.g., 210' and 220') (also referred to herein as "signal electrode buses") are then formed using conventional metallization techniques, along with contacts (e.g., 25') which connect the column buses (e.g., 210') to their proper FET drain regions (e.g., 21').
Another oxide layer 74 is then formed over the oxide layer 73, as well as over the column buses (e.g., 210' and 220'). Using conventional techniques, holes (e.g., 27" and 242") are then formed in the oxide layers 71, 73 and 74 which extend from the top surface of the oxide layer 74 down to the source regions of the FETs and polysilicon storage capacitor electrodes (e.g., 23' and 22', respectively).
Reflective electrodes (e.g., 240' and 340') are then formed using conventional metallization techniques, along with vias (e.g., 27' and 242') which connect the reflective electrodes (e.g., 240') to their respective source regions and storage capacitor electrodes (e.g., 23' and 22', respectively).
With the polysilicon storage capacitor electrodes (e.g., 22') thus connected to the source regions (e.g., 23') of their respective FETs through their respective reflective electrodes (e.g., 240'), the storage capacitors (e.g., 12 in FIG. 1) are then completed by grounding the substrate 70 which acts as a second electrode for each of the storage capacitors (e.g., 12 in FIG. 1), and using the field oxide layer 71 as a dielectric medium.
Although only a few representative pixels and their related drive circuitry have been shown in FIGS. 1, 2A, 2B and 2C, it is to be understood that active matrix liquid crystal displays may readily have thousands of such pixels organized in a matrix of rows and columns. When the number of such pixels is large in any given row of pixels, the resistive and capacitive load built up along the length of a polysilicon gate bus such as that illustrated as gate bus 100' in FIG. 2A-2C, can cause the last pixel in that row to switch ON and OFF much slower than the first pixel in that row. This transmission line effect optically results in an undesirable fading of contrast along the row of pixels which is further aggravated as the pixel size and pitch and consequently, the required width W of the polysilicon gate bus (e.g., 100') gets smaller.
To avoid the aforedescribed transmission line and resulting fading or non-uniform pixel contrast problem, the gate bus 100' might be formed of metal instead of polysilicon material. A metal gate bus, however, would require processing a third level of metallization which is very expensive using current processing technology. Not only would a third metallization layer require an additional oxide layer forming step, but it would also require additional photomasking and etching steps to form holes and contacts through the additional oxide layer down to previously deposited gate electrodes formed over the FET channel regions. Such an approach would result in significantly lower yields than the aforedescribed polysilicon gate bus approach.